Circuit arrangement for controlling a high side cmos transistor in a high voltage deep sub micron process

ABSTRACT

The present invention relates to a circuit arrangement, which is used for controlling a high side CMOS transistor (M 1 ) in a high voltage deep sub micron process. To provide a circuit arrangement for switching a high side CMOS transistor (M 1 ) in a circuit having a very thin gate oxide, which is in particular produced by a deep sub micron process a circuit arrangement is proposed for controlling a high side CMOS transistor (M 1 ) in a high voltage deep sub micron process, wherein the high side CMOS transistor (M 1 ) is coupled between a high side voltage potential (Vbat) and a control output (OUT) for switching an external device, the high side CMOS transistor (M 1 ) is controlled at its gate by a reference potential (Vbat-Vref), which is provided by a high side voltage reference ( 11 ) having a capacitor (C 1 ), which is charged for switching on and discharged for switching off the high side CMOS transistor (M 1 ).

The present invention relates to a circuit arrangement, which is used for controlling a high side CMOS transistor in a high voltage deep sub micron process. The high side CMOS transistor is used for switching high voltages. But in a high voltage deep sub micron process the maximum allowed voltage across the gate oxide and the source of the high side transistor is limited to be smaller than a predetermined voltage rating, e.g. 3,3V while the voltage with respect to the substrate of the circuit arrangement can vary from 5V to 100V, which is the high side voltage. In an automotive area, the battery voltage of a car is between 5V and 60V. This voltage may appear when the battery is charged and the connection to the battery is suddenly interrupted, a so-called load dump.

In other words, the supply voltage of the high side CMOS transistor exceeds the maximum voltage rating of the gate oxide. For limiting the gate voltage for reliable operating the high side CMOS transistor, an accurate voltage reference is required providing a voltage within the voltage rating of the gate oxide. This high side voltage reference must be accurate and low current. Such accuracy is needed due to the low tolerance of the maximum voltage rating of the gate oxide of the high side CMOS transistor. Additionally, the circuit should consume as less current as possible because of reliability reasons. In the automotive industry, circuits can be fed directly from the battery. Therefore, they are continuously under voltage during the total lifecycle of a car. Thus, it is strongly required to reduce the current as much as possible especially for chips having a very thin gate oxide as in case for a deep sub micron process.

A known solution for providing a high side voltage reference is a floating DC voltage source. However, such solution is not limited in their current consumption. Such floating DC voltage source is illustrated in FIG. 1 in an abstract from.

Therefore, the object of the present invention is to provide a circuit arrangement for switching a high side CMOS transistor in a circuit having a very thin gate oxide, which is in particular produced by a deep sub micron process.

The object is solved by the features of the independent claims.

The invention bases on the idea to provide a high side voltage reference having a low current consumption. By providing such high side reference voltage it is possible to control the high side CMOS transistor without providing a circuit having a high current consumption. In particular, it is proposed to control the high side CMOS transistor at its gate with a high side reference potential including a capacitor which is charged or discharged and thereby switching on/off the high side CMOS transistor.

Due to the use of the capacitor, it is possible to create an accurate biasing voltage at the reference potential for switching on the high side CMOS transistor. The capacitor is charged by a current only with few pulses. The high side voltage reference used for the inventive circuit may include a resistor connected to the high side potential and the reference potential. The capacitor is coupled in parallel to the resistor between the high side voltage and the reference potential. A diode is coupled between the resistor and the capacitor at the reference potential for preventing a discharge of the charged capacitor during the off-periods of the pulsed current source.

In preferred embodiment it is proposed that the current source includes a first and a second switch, which are controlled to charge/discharge the capacitor and thereby to switch on/off the high side CMOS transistor. The first switch is connected to the cathode of the diode and to the first resistor of the high side voltage reference. The second switch is used for discharging the capacitor. The first and second switches are controlled by using a first and a second pulse, which are generated by an external clock. The duty cycle for the first and second pulses is very low. Thus, the effective current running through the circuit is drastically reduced.

In the preferred embodiment, the first switch is realized as an NMOS transistor, which is switched on by the first pulse, which is applied to the gate of the first NMOS transistor. The NMOS transistor is creating a pulsed current flowing through the resistor, the diode and the capacitor for charging the capacitor. By applying the first pulses to the first NMOS transistor an accurate biasing voltage is created at the reference potential, which is necessary for reliable switching on the high side CMOS transistor. Due to the use of the capacitor, it is possible to provide this accurate biasing voltage, which is within the voltage rating for the gate oxide. Thereby, the gate oxide of the high side CMOS transistor is prevented for being destroyed due to higher voltages.

The second switch is also realized as NMOS transistor, which is switched on by a second pulse at its gate, wherein by switching on the second pulse at the second NMOS transistor, the high side CMOS transistor is switched off. In particular, it is proposed for reliable discharging the capacitor to provide a further resistor between the high potential and the reference potential and to provide a third transistor between the high side potential and the reference potential. By switching off the first transistor and by providing the second pulse at the gate of the second transistor, a voltage pulse is created across the further resistor between the high side potential and the reference potential. Thus, the third transistor between the high side potential and the reference voltage is driven and thereby discharging the capacitor resulting in a switching off of the high side CMOS transistor.

In a preferred embodiment of the invention, the first and second pulses used for controlling the first and second switches are identical in their duty cycle. Alternatively, it may be advantageous that the first and second pulses have different forms. In particular, it may be required to charge the capacitor after switching off the high side transistor faster. Thus, it is required to extend the first pulse in time for charging the capacitor a longer time.

In a further preferred embodiment, it is proposed to use a level shifter as a high side voltage reference for providing the reference potential.

In the following preferred embodiments of the invention are explained in more detail by use of the following figures in which:

FIG. 1 shows a schematic circuit diagram of a floating DC voltage source for controlling the high side CMOS transistor;

FIG. 2 shows a first embodiment according to the invention;

FIG. 3 shows a realization of the first embodiment according to invention;

FIGS. 4 a, b illustrate timing diagrams showing the first and second pulses for charging and discharging the capacitor;

FIG. 5 shows second embodiment according to the present invention.

FIG. 1 shows a schematic circuit diagram, in which a high side CMOS transistor M1 is coupled to the high side voltage Vbat and an external output OUT, wherein the gate of the high side CMOS transistor M1 is controlled by a high side voltage reference 11. The high side CMOS transistor M1 is used for switching high voltages. Since the gate source voltage of this high side CMOS transistor MI has a limited voltage rating an accurate high side voltage reference 11 is required to operate the high side CMOS transistor M1. This high side voltage reference 11 should consume as less power as possible, since it should be used in automotive area. Integrated circuits of a car may be coupled to the power supply (Vbat) during the whole lifetime of a car. Therefore, the power consumption should be reduced as much as possible.

In more detail, a circuit diagram according to the invention is illustrated in FIG. 2. There is a high side CMOS transistor M1, which is coupled between the high side voltage Vbat, and an external output OUT. The high side voltage reference 11 is composed of a resistor RI connected to the high side voltage Vbat and the reference potential and a capacitor C1 having a capacity of 1 to 50 pF. The capacitor C1 is charged/discharged and thereby a switching on/off of the high side CMOS transistor M1 is achieved. The capacitor C1 is connected to the high side voltage Vbat and the reference potential. For charging the capacitor C1, a pulsed current source 21 is used. For preventing a current flow during off cycles of the pulsed current source causing a discharge of the capacitor C1, a diode D is connected between the capacitor C1 and the current source 21.

A first embodiment of a circuit arrangement according to the invention is explained in more detail with reference to FIG. 3. Therein, the high side CMOS transistor M1 is connected between the high side voltage Vbat and the external output OUT. Further, there is a high side voltage reference 11 comprising the resistor R1, the capacitor C1 and the diode D between the resistor R1 and the capacitor C1. Additionally, there is the current source 21 comprising a first switch M3 and a second switch M4. The first switch M3 is realized as NMOS transistor coupled between the reference potential and ground via a further resistor R3. The first switch M3 is pulsed by a first pulse A. A second switch M4 is pulsed by a second pulse B, wherein a further resistor R4 is connected between the source of the second switch M4 and ground. A third transistor M2 is coupled between the high side voltage Vbat and the reference potential, wherein the gate of the third transistor M2 is connected to second switch M4. A further resistor R2 is coupled between the high side voltage Vbat and the second switch M4 for providing a voltage for controlling the gate of the third transistor M2.

Now, the functioning of the circuit diagram as shown in FIG. 3 is explained by use of FIG. 4. When applying the first pulse A at the gate of the first switch M3, the peak voltage across the resistor R1 is determined by the peak voltage at the gate of the first switch M3 and the ratio of the resistors R1 and R3. By applying the pulse A at the gate of the first switch M3 the capacitor C1 is charged to an accurate voltage, which can drive the gate of the high side CMOS transistor M1. Thus, the high side CMOS transistor M1 could be switched on by use of an accurate voltage provided by the charge of the capacitor C1. For turning off the high side CMOS transistor M1, a first pulse A at the first switch M3 is switched off and a second pulse B is provided at the gate of the second switch M4 instead. This creates accurate voltage pulses across the resistor R2 between the high voltage potential Vbat and second switch M4 which drives the third transistor M2 to discharge the capacitor C1 and thereby switching off the high side CMOS transistor M1. Both switches M3, M4 are driven with a very low duty cycle as can be seen in FIG. 4 a for charging the capacitor C1 or to keep the capacitor C1 discharged even in the presence of leakage currents. FIG. 4 a illustrates the voltage waveforms on nodes A, B, C as shown in FIG. 4 a. As long as there is a voltage drop across capacitor C1 it is charged. When switching off the first pulse A and switching on the second pulse B instead there is no voltage drop across C1 anymore. Thus, the capacitor C1 is discharged resulting in a switching off the high side CMOS transistor M1.

As shown in FIG. 4 a, the pulses for the first and second switch M3 and M4 having an identical duty cycles. However, it is possible to use different pulse forms as shown in FIG. 4 b. Especially, when first switching on the first switch M3, after the second switch M4 was operated, the capacitor C1 is fully discharged and it is advantageous to switch on the first switch M3 for a longer time in order to charge capacitor C1 more quickly. This could be easily seen in FIG. 4 b. The capacitor C1 is charged during one long pulse or several short pulses with a predetermined duty cycle as illustrated in FIG. 4 b. After C1 is charged, a recharging with a low duty cycle with short pulses is necessary. Recharging is necessary because leakage currents are always present in silicon processes, which can discharge the capacitor C1 slowly. Therefore, a controlled discharge of the capacitor C1 would ideally be done with one pulse on the second switch M4, wherein the length of the pulse needs not to be related to the length of the pulse on M3 which charges C1.

In case of identical pulses the pulse widths for pulses A and B maybe in the range of 0,1-1 μs, wherein the distance between the pulses maybe 0,1-1 ms. For FIG. 4 b the same values could be used, wherein the longer pulse of pulse A maybe three times longer than the short pulses of M4.

FIG. 5 illustrates a second embodiment of the circuit arrangement according to the present invention. FIG. 5 illustrates a high side voltage reference 11 providing the reference potential for switching on/off the high side CMOS transistor M1. There is an external voltage source V_(ex) providing a predetermined voltage e.g. 3,3V. By using a double-switch Q1, the external voltage source V_(ex) can be connected to a second capacitor C0 for charging this second capacitor C0. The second capacitor C0 may be connected to the high voltage Vbat and to ground by the switches Q1 or Q2, respectively. The switch Q2 is used for connecting the capacitor C0 with the high side voltage Vbat. The second capacitor C0 is coupled in parallel to the first capacitor C1. At the reference potential, there is a diode D for preventing a discharge of the first capacitor C1. When the switch Q1 is closed and the switch Q2 is opened, the second capacitor C0 is charged at 3.3V. When switch Q2 is closed and switch Q1 is opened, the voltage drop on the second capacitor C0 is still 3.3V. The voltage drop on the first capacitor C1 is then lifted to the high voltage Vbat-3.3V. Again the diode D servers to make sure that current can flow back to C1 to discharge the first capacitor C1. By charging/discharging the first capacitor C1 the high side CMOS transistor M1 could be switch on/off. When the switches Q1 and Q2 are controlled to discharge the first capacitor C1, the high side CMOS transistor M1 is switched off. By providing the low current high side voltage reference according to the second embodiment, it is possible to switch on/off the high side CMOS transistor M1 with a limited voltage rating which is not destroying the very thin gate oxide of the high side CMOS transistor MI that is produced in deep sub micron process.

A clear advantage of the second embodiment over the first is that there is no power waste, when neglecting parasitic capacitances. When switched on the first embodiment always consumes power even when the capacitor C1 that stores the high-side voltage does not need to be charged. In contrast, the second embodiment only supplies the charge needed to create the required voltage. 

1. Circuit arrangement for controlling a high side CMOS transistor in a high voltage deep sub micron process, comprising: a high side voltage potential; a control output; an external device: a reference potential; a high side voltage reference, wherein the high side CMOS transistor is coupled between the high side voltage potential and the control output for switching the external device, wherein the high side CMOS transistor is controlled at its gate by a reference potential which is provided by the high side voltage reference having a first capacitor, which is charged for switching on and discharged for switching off the high side CMOS transistor.
 2. The circuit arrangement according to claim 1, wherein the high side voltage reference comprises a resistor and a second capacitor connected to the high side potential, wherein a diode is coupled between the resistor and the second capacitor at the reference potential.
 3. The circuit according to claim 1, further comprising a pulsed current source for charging/discharging the first capacitor, including a first switch, connected to the cathode of a diode and resistor of the high side voltage reference, and a second switch connected to a third switch for controlling the reference potential.
 4. The circuit arrangement according to claim 3, wherein the first and the second switches are controlled to charge/discharge the first capacitor and to switch on/off the high side CMOS transistor.
 5. The circuit according to claim 4, wherein the first switch is a NMOS transistor, which is switched on by a first pulse applied to the gate for creating a pulsed current flowing through the resistor, the diode and the first capacitor for charging the first capacitor and for creating an accurate biasing voltage at the reference potential for switching on the high side CMOS transistor.
 6. The circuit according to claim 5, wherein the second switch is a NMOS transistor, which is switched on by a second pulse for switching off the high side CMOS transistor.
 7. The circuit according to claim 6, wherein by switching off the first switch and by providing the second pulse at the gate of the second switch a voltage pulse is created across a second resistor between the high side potential and the second switch for driving the third switch to discharge the first capacitor and thereby switching off the high side CMOS transistor.
 8. The circuit according to claim 7, wherein the first and second pulses provided to the first and second switches are identical in their duty cycle.
 9. The circuit according to claim 7, wherein the first and second pulses provided to the first and second switches have different duty cycles.
 10. The circuit according to claim 9, wherein after the first capacitor is discharged by the second switch, the first pulse is activated for a longer period than a period for accelerating charging of the first capacitor.
 11. The circuit according to claim 1, wherein the high side voltage reference comprises an external voltage source and a third capacitor wherein the first and third capacitor are coupled in parallel between the high side voltage potential and the reference potential wherein a diode is connected between the first and third capacitor at the reference potential, wherein the charging/discharging of the first and third capacitor is controlled by using fourth and fifth switches for switching on/off the high side CMOS transistor.
 12. The circuit arrangement according to claim 11, wherein a level shifter is used as a high side voltage reference for providing the reference potential. 